1. Field of the Invention
The present invention generally relates to integrated circuits. More particularly, the present invention provides a structure and method for providing gate leakage isolation locally within analog circuits.
2. Related Art
With succeeding generations of semiconductor manufacturing technology, gate insulator (e.g., oxide) thicknesses have decreased dramatically, in part to support high performance, low power digital systems. Unfortunately, as gate oxide thicknesses decrease, local defects in the gate oxide become a larger factor in gate leakage within a semiconductor device. While gate leakage may be viewed as an unavoidable nuisance in digital systems, it may create functional and performance issues for analog circuits, such as Phase-Locked-Loops (PLLs), which are routinely integrated within a semiconductor device.
The functional sensitivity of PLLs or similar circuits as a result of gate leakage is largely due to the use of thin-oxide capacitors in the construction of a PLL loop filter, which stores the control voltage critical to loop frequency stability. While oxide defect densities are typically reduced over time in a given technology, it has been estimated that in early production of new technologies, oxide defects, otherwise known as “pinholes,” may affect a measurable percentage of unit capacitors within a PLL loop filter, resulting in an unacceptable reduction in manufacturing yield. An illustrative thin-oxide capacitor 10 is illustrated in FIG. 1 (no pinhole) and FIG. 2 (with pinhole 12 and resultant gate leakage current 14). As shown in the illustrative PLL circuit 16 depicted in FIG. 3, the gate leakage current 14 causes a current pump offset 18, which results in a phase error 20 between the reference signal (Ref) and feedback signal (Fbk) of the PLL circuit 16, thus negatively affecting the performance of the PLL circuit 16.